Congratulations to Ms. Nguyen for acceptance of her paper titled “An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning” for publication and presentation at ISCAS 2022! Looking forward to interacting with participants in Austin, Texas (USA) in May!

Congratulations to Dr Panpan Zhang on her appointment as an Assistant Professor in the Department of Electrical Engineering at Shanghai Jiao-Tong University! She will begin her appointment in August 2021.

Ms Nguyen Thao will be presenting two of her works at the International Conference on Neuromorphic Systems (ICONS) 2021! Watch out for the presentations titled “Connection Pruning for Deep Spiking Neural Networks with On-Chip Learning” and “Instruction Set for a Neuromorphic Co-Processor with On-Chip Learning”.

Her recorded presentation on “Connection Pruning for Deep Spiking Neural Networks with On-Chip Learning” is available to registrants to ICONS 2021 at this link.

Congratulations to Jeffrey Low for coming in 1st place overall in the ECE FYP / Capstone e-Poster Competition! His project poster is titled “Neural Network Accelerator with Parameterized Artifacts on FPGA” and was jointly supervised by Dr Kelvin Fong Xuanyao from NUS ECE, and Dr Han Tao from the Defense Science Organization (DSO), Singapore.

Our paper titled “FANTASI: a novel devices-to-circuits simulation framework for fast estimation of write error rates in spintronics” will be presented by lead author Pavan Kumar at the 2018 International Conference on Simulation of Semiconductor Processes And Devices (SISPAD). See you on 24 to 26 September 2018 at the AT&T Executive Education, Hotel & Conference Center in Austin, Texas, USA.

The SEEDER group is recruiting members for the following projects. All applicants must be proficient in oral and written English. Interested candidates may apply by sending their resume or CV to kelvin dot xy dot fong at nus dot edu dot sg.

Reconfigurable Interconnect Scheme Using RRAM Devices

An open position is available for post-doctoral candidates with the following qualifications. Qualified applicants must possess a Ph.D. upon joining.

1. Research Fellow (TCAD Modeling of Multi-terminal RRAM Device Structures)
   • Ph.D. in Electrical Engineering, Materials Science, Physics (Applied) or Mathematics (Applied)
   • The objective of the candidate is to:
     • Develop a COMSOL based TCAD simulator to simulate the behavior of multi-terminal RRAM devices
     • Use the developed TCAD simulator to explain and predict electrical measurements obtained from devices that are fabricated in the laboratory
     • Develop Verilog-AMS based compact models for various multi-terminal RRAM device structures and predict performance of the RRAM-based interconnect fabric

Skyrmionic Computing Microarchitecture

There are two open positions for post-doctoral candidates and an opening for a PhD student who meet the following requirements. Qualified applicants for post-doctoral positions must possess a Ph.D. upon joining.

1. Research Fellow (Skyrmionic Computing Architecture)
   • Ph.D. in Electrical or Computer Engineering, or Computer Science (newly graduated to two years post-doctoral experience)
   • The objective of the candidate is to:
     • Map cortical algorithms (feedforward, feedback and both online and offline learning) to the behavior of spintronic devices based on skyrmions
     • Develop a simulator for the hardware architecture to prove its operation
     • Evaluate the performance of the hardware architecture on a variety of cognitive tasks
2. Research Fellow (Modeling Interactions Between Spin-Waves and Skymions)
   • Ph.D. in Electrical Engineering, Materials Science, Physics (Applied) or Mathematics (Applied)
   • The objective of the candidate is to:
     • Perform micromagnetic simulation studies of the interaction between spin waves and skyrmions in magnetic thin films
     • Propose designs for the hardware that uses our Skyrmion-based Computing Microarchitecture
     • Identify design challenges in the design of hardware that uses our Skyrmionic Computing Microarchitecture and propose solutions to overcome them
3. PhD Student (Approaches to Implementing Skyrmionic Computing Microarchitecture)
   • Good in oral and written English
   • The objective of the candidate is to:
     • Develop device and circuit models to simulate the operation of Skyrmion-based device structures
     • Develop an understanding of the interactions between device parameters and “circuit performance”
     • Explore various design challenges in the design of hardware that uses our Skyrmionic Computing Microarchitecture

The SEEDER group is seeking new members. Openings are available for new PhD students, post-doctoral fellows who recently obtained a PhD, and graduate/undergraduate students interested in participating research projects within the SEEDER group. Please contact or send your resume or CV to Dr Kelvin Fong.

Dr Kelvin Fong Xuanyao has joined the Department of Electrical & Computer Engineering at the National University of Singapore as an Assistant Professor and established the Semiconductor and Emerging Electronic Devices Exploratory Research Group.