Scalable Energy Efficient Hardware Accelerators

The demand for more computational power has exploded in the era of artificial intelligence. The traditional Moore’s law downscaling of device geometry is insufficient to meet the growing demand for more computational power sustainably and economically.

To address this challenge, the SEEDER Group is very interested in algorithm-technology co-design of electronic systems. We believe that co-design of algorithms with compute hardware and the underlying device technologies will yield electronic systems that far outperform CMOS electronics in domain-specific applications. Thus, we explore device concepts, circuits, microarchitectures and system architectures, and algorithms to gain a holistic picture of the key research challenges. Research topics along this research thrust include:

• Novel device concepts for scalable and energy efficient computing
• Design of hardware-friendly algorithms
• Design of hardware accelerator microarchitectures
• Technologies for wafer-scale multi-chiplet accelerators