Software-Defined Accelerator: Coarse-Grained Reconfigurable Array
CGRAs were proposed around 2000, to accelerate compute-intensive inner loops of Digital Signal Processing(DSP) applications. A CGRA is essentially a set of processing elements (PE) arranged in a grid with each PE connected to its neighbors. Each PE typically consists of a simple ALU, a register file, and a control memory to store configuration information (instructions). An on-chip multi-bank scratchpad memory (SPM) feeds data to the entire array during execution.
CGRAs are statically scheduled with the compiler targeting frequently executed loops for acceleration, mapping the operations onto individual PEs, and configuring the ALUs and inter-PE interconnects appropriately to handle dependencies among the operations. The schedule covers all the PEs and interconnects for a fixed number of cycles per loop iteration and the schedule is repeated for all iterations. Thus the schedule is defined along with both the spatial (PEs) and the temporal (cycles) dimensions.
The objective of this project is to push the boundaries of the architecture and compilers for coarse-grained reconfigurable arrays to enable promising benefits, such as superior energy efficiency, compared to other processor architectures. The inherent ability of CGRAs to perform application synthesis in a time predictable manner enables them to remove unnecessary overheads that would otherwise be there to perform synchronization and conflict resolution. However, this leads to a complicated compilation process that ultimately could lead to performance drawbacks. In our research group, we employ hybrid hardware-software mechanisms that introduce novel architectural features that directly translate to improvements in the compilation process that brings performance and energy benefits.
Tools
Morpher: An Open-Source Compilation Framework for CGRA
A CGRA compiler is generally tied to a particular architecture. At present, there does not exist a tool that allows the designer to easily specify a variety of architectural features in a unified fashion and automatically instantiate, corresponding to the specified design, a quality compiler (in terms of both compilation time and mapping quality). This unavailability of tools makes architectural and compiler research for CGRA challenging. We present Morpher, a powerful, integrated compilation framework for CGRA, that fills this gap with a flexible approach enabling easy specification of complex architectural features and automated modeling of these features in efficient compiler.
Publications
- [TCAD’21] ChordMap: Automated Mapping of Streaming Applications onto CGRA
- [DATE’21] HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
- [ICCAD ’19] 4D-CGRA : Introducing the branch dimension to spatio-temporal application mapping of CGRAs
- [CASES/ACM TECS ’19] CASCADE: High Throughput Data Streaming via Decoupled Access/Execute CGRA.
- [DAC ’18] DNestMap : Mapping Deeply-Nested Loops on Ultra-Low Power CGRAs
- [DAC ’17] HyCUBE : A CGRA with Reconfigurable Single-cycle Multi-hop Interconnect
- [TRETS ’14] Graph Minor Approach for Application Mapping on CGRAs