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Résumé

  • Education
    • Direct Ph.D. in Electrical Engineering
      • August 2006 – December 2014
      • Purdue University, West Lafayette, IN, USA
      • Advisor: Professor Kaushik Roy
      • Areas:
        • (Primary) VLSI Circuit Design,
        • (Secondary) Microelectronics and Nanotechnology
      • Completed Graduate Coursework:
        • Advanced VLSI Design (ECE695KR)
        • Digital (ECE559) and Analog (ECE595B) VLSI Design
        • Interconnect Modeling (ECE670)
        • Introduction to Algorithms (ECE608)
        • Semiconductor Fundamentals (ECE606)
        • Advanced Semiconductor Devices (ECE612, ECE654)
        • Nanoelectronics (ECE659)
        • Introduction to IC /MEMS Fabrication (ECE557)
        • Linear Algebra, Advanced Math for Engineers
      • GPA: 3.80/4.00
    • Bachelor of Science in Electrical Engineering (Distinction)
      • August 2003 – May 2006
      • Purdue University, West Lafayette, IN, USA
      • GPA: 3.86/4.00
      • Dean’s List and Semester Honors for every semester
  • Research Experience
    1. Modeling and Simulation of Spintronic Devices for Neuromorphic Computing
    2. Exploring, Modeling and Simulation of Domain Wall Motion Devices for Neuromorphic and Analog Applications
    3. Modeling and Simulation of Spintronic Devices Switched by Femtosecond Laser Pulses
    4. Modeling and Simulation of spin-torque oscillators and exploration of applications
    5. Designing Ultralow Power and Robust Spin-Transfer Torque Magnetic Random Access Memory for On-chip Cache Applications (Ph.D.)
    6. Explored Design Methodologies for Nano-magnet Based Logic (Ph.D.)
    7. Designing Ferroelectric Capacitor Random Access Memories (Ph.D.)
    8. Analyzed Carbon Nanotubes for Ultra-low Power Digital Circuit Applications (Ph.D.)
  • Technical Skills
    • Programming Languages
      • Proficient in: Perl, Verilog, VHDL
      • Familiar with: Tcl/Tk, C/C++, Fortran, Go, HC12 Assembly Language
    • Software and Technologies
      • Tools proficient in: CUDA, MATLAB, HSPICE, ModelSim, Cadence Tools (ICFB, Virtuoso Spectre), Object-Oriented MicroMagnetics Framework (OOMMF), MuMax, Microsoft Office Suite
      • Familiar platforms: Sun Solaris, Microsoft Windows, Red Hat Linux, Ubuntu/Kubuntu Linux
    • Hardware
      • FreeScale HC12 Microcontroller
      • Tektronics Logic Analyzer
      • Agilent and HP Oscilloscopes, Digital Multimeters and Signal Generators
  • Work and Teaching Experience
    1. Research Scientist
      • June 2015 – Present
      • Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), Singapore
      • Assisting in the research and development of spin-transfer torque (STT)-MRAM
    2. Postdoctoral Research Assistant
      • August 2014 – May 2015
      • Purdue University, West Lafayette, IN
      • Assisted Professor Kaushik Roy in academic research
      • Explored applications for, and modeling and simulation of spin-based devices and other emerging technologies
    3. Graduate Research Assistant
      • August 2007 – August 2014
      • Purdue University, West Lafayette, IN
      • Assisting Professor Kaushik Roy in academic research
      • Worked on simulation and design of robust spin-transfer torque magnetic random access memories
    4. Co-op Engineer
      • January 2007 – August 2007
      • Advanced Micro Devices, Inc., Boxborough, MA
      • Aided testing and developed Construction Design Checks for core circuit designs and layout
      • Debugged electromigration calculator script for budgeting and estimating electromigration in core circuit blocks
      • Performed timing and noise margin analyzes for standard cell libraries
      • Debugged Perl-based CAD tool that generates circuit/SPICE templates for other analysis tools (logical equivalence checks, etc.)
      • Analyzed repeater networks for aggressive design of core clock grid to meet area, power, performance and electromigration specifications
    5. Graduate Teaching Assistant
      • August 2006 – December 2006
      • Assisted Professor Eric S. Furgason in teaching Linear Circuit Analysis II (ECE202)
      • Chief responsibility was to hold office hours to answer students’ questions regarding homework, exams and to clarify doubts and questions on course material
    6. Undergraduate Tutor
      • August 2004 – May 2006
      • Purdue University, West Lafayette, IN
      • Tutor students in Linear Circuit Analysis I and II (ECE 201, ECE202)
  • Certifications
    • Fundamentals of Engineering
  • Society Memberships
    • Student member of the Institute of Electrical and Electronics Engineers (IEEE)
    • Student member of Semiconductor Research Corporation (SRC)
    • Student member of Nano-Research Initiative (NRI)
  • Awards and Recognitions
    • Received ‘Best Paper Award’ at International Symposium for Low Power Electronics Design (ISLPED) 2006 for the paper titled “Analysis of super cut-off transistors for ultralow power digital logic circuits“
    • Received ‘AMD Design Excellence Award’ for the Advanced VLSI Design class (ECE695KR, 2008) at Purdue University for the project titled “Complementary Ferroelectric Capacitor (CFC) logic: application to TAG RAM”
    • Received ‘Best Paper in Session Award’ at SRC Techcon 2009 for the paper titled “A comprehensive nano-magnet based logic synthesis for ultra-low power digital systems”
  • Course Projects
    • Design of I2C to USB2.0 transceiver using VHDL
    • Implementation of active and switched capacitor RC filter design using high-swing, low-voltage operational amplifier
    • Design of voltage-scalable finite-field multiplier using adaptive cycle operation
    • Design of Complementary Ferroelectric Capacitor (CFC) logic for application in TAG RAM
    • Implementation of a fast low-power, skew-constrained clock tree synthesis tool
    • Fabrication of PMOS transistor
    • Fabrication of MEMS cantilever

3 Comments on “Résumé”

  1. Hi, this is Youngtak Lee, currently a PhD student at the Georgia Institute of Technology. I have lately been scrutinizing your codes uploaded on nanohub which explains your work of the operation of an MTJ device in a MTJ/CMOS hybrid modeling. I have tried to run your codes on hspice but it gives me an error message that states as follow:
    **error** (.mtj_libs_encoded/MTJ.lib).lib entry “NRL_MTJS” cannot be found.

    Could you please explain to me how to fix the problem and run it successfully?

    Thanks,

    Best regards,

    Reply

    • Hi Youngtak,

      It looks like the problem is that you are running a version of HSPICE that cannot read the library. We have uploaded the libraries for three different versions of HSPICE onto the NanoHub.org site. Please download the library for your version of HSPICE and test with the example that is available on NanoHub.

      Best,
      Xuanyao (Kelvin) Fong

      Reply

  2. Hi Xuanyao,

    I faced with the same problem while trying to import your models in Agilen ADS (Keysight). The error message says: “No library named `NRL_MTJS’ was found in the HSPICE file `.././mtj_libs_encoded/./MTJ.lib’.” After that, I gave it a shot and tried to use all three versions of your models. Unfortunately, nothing worked.

    Any suggestions?

    Reply

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