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Conference Presentations

2021

  1. T. N. N. Nguyen, B. Veeravalli, and X. Fong, “Connection Pruning for Deep Spiking Neural Networks with On-Chip Learning,” in International Conference on Neuromorphic Systems 2021 (ICONS 2021), July 27-29, 2021, Knoxville, TN, USA. ACM, New York, NY, USA 8 Pages. doi:10.1145/3477145.3477157 [PDF]
  2. T. N. N. Nguyen, B. Veeravalli, and X. Fong, “Instruction Set for a Neuromorphic Co-Processor with On-Chip Learning,” to appear in International Conference on Neuromorphic Systems 2021 (ICONS 2021), Jun. 2021 (Poster)
  3. K. Cho, X. Fong, and S. K. Gupta, “Exchange‐Coupling‐Enabled Electrical‐Isolation of Compute and Programming Paths in Valley‐Spin Hall Effect based Spintronic Device for Neuromorphic Applications,” in Device Research Conference 2021, Jun. 2021, (Poster)

2020

  1. A. T. Do, X. Fong, and F. Li, “Aggressive Leakage Current Reduction for Embedded MRAM Using Block-Level Power Gating,” 46th Annual Conference of the IEEE Inndustrial Electronics Society (IECON 2020), pp. 2249-2254, Nov. 2020, doi:10.1109/IECON43393.2020.9254774 [PDF]

2019

  1. S. Samanta, K. Han, S. Xu, X. Gong, and X. Fong, “Impact of Ti Interfacial Layer on Resistive Switching Characteristics at sub-µA Current Level in SiOx-Based Flexible Cross-Point RRAM,” in IEEE International Conference on Flexible and Printable Sensors and Systems (FLEPS), Jul. 2019, pp. 1-3, doi:10.1109/FLEPS.2019.8792259 [PDF]

2018

  1. S. Samanta, K. Han, S. Xu, X. Gong, and X. Fong, “Digital and Analog Resistive Switching Characteristics under 200 nA Current Level using Novel Ni/SiOx/W 16×16 Cross-point Architecture,” in Proc. of 49th IEEE Semiconductor Interface Specialists Conference (SISC), Dec. 2018, 5.1, [PDF]
  2. V. P. K. Miriyala, X. Fong, and G.-C. Liang, “FANTASI: A Novel Device‐to‐Circuits Simulation Framework for Fast Estimation of Write Error Rates in Spintronics,” in Proc. of International Conference on Simulation of Semiconductor Processes and Devices 2018, Sep. 2018, pp. 53-57, doi:10.1109/SISPAD.2018.8551656 [PDF]
  3. S. Deb, A. Chattopadhyay, A. Basu, and X. Fong, “Domain Wall Motion-based XOR-like Activation Unit with A Programmable Threshold,” in Proc. of International Joint Conference on Neural Networks 2018, Jul. 2018, pp. 463-470, doi:10.1109/IJCNN.2018.8489146 [PDF]
  4. J. Deng, X. Fong, P. Zhang, and G.-C. Liang, ” Layout-awareness of Three-terminal pMTJ Switched by Electric Field without External Magnetic Field,” IEEE Silicon Nanoelectronics Workshop (SNW), Jun. 2018, (Poster)

2016

  1. G. Narasimman, S. Roy, X. Fong, K. Roy, C.-H. Chang, and A. Basu, “A Low-voltage, Low Power STDP Synapse Implementation using Domain-wall Magnets for Spiking Neural Networks,” in Proc. of 2016 IEEE Int. Symposium on Circuits and Systems (ISCAS), May 2016, pp. 914-917, doi:10.1109/ISCAS.2016.7527390 (Invited Paper) [PDF]

2015

  1. Z. Pajouhi, X. Fong, and K. Roy, “Device/Circuit/Architecture co-design of reliable STT-MRAM,” in Proc. of IEEE/ACM Design, Automation &Test in Europe (DATE), Mar. 2015, pp. 1437-1442, doi:10.7873/DATE.2015.0145 [PDF]
  2. K. Yogendra, M.-C. Chen, X. Fong, and K. Roy, “Domain wall motion based low power hybrid spin-CMOS 5-bit Flash analog data converter,” in Proc. of 16th IEEE Int. Symposium on Quality Electronic Design (ISQED), Mar. 2015, pp. 604-609, doi:10.1109/ISQED.2015.7085496 [PDF]
  3. A. Ranjan, S. Venkataramani, X. Fong, K. Roy, and A. Raghunathan, “Approximate storage for energy efficient spintronic memories,” in Proc. of IEEE/ACM Design, Automation & Test in Europe (DATE), Mar. 2015, pp. 1-6, doi:10.1145/2744769.2744799 [PDF]
  4. R. Venkatesan, S. Venkataramani, X. Fong, K. Roy, and A. Raghunathan, “Spintastic: Spin-based stochastic logic for energy-efficient computing,” in Proc. of IEEE/ACM Design, Automation & Test in Europe (DATE), Mar. 2015, pp. 1575-1578, [PDF]

2014

  1. X. Fong, M.-C. Chen, and K. Roy, “Generating true random numbers using on-chip complementary polarizer spin-transfer torque magnetic tunnel junctions,” in Proc. of 72nd Device Research Conf. (DRC), Jun. 2014, pp. 103-104, doi:10.1109/DRC.2014.6872318 [PDF]
  2. L. Zhang, X. Fong, C. H. Chang, Z. H. Kong, and K. Roy, “Highly reliable memory-based physical unclonable function using spin-transfer torque MRAM,” in Proc. of 2014 IEEE Int. Symp. on Circuits and Systems, Jun. 2014, pp. 2169-2172, doi:10.1109/ISCAS.2014.6865598 [PDF]
  3. L. Zhang, X. Fong, C. H. Chang, Z. H. Kong, and K. Roy, “Feasibility study of emerging non-volatile memory based physical unclonable functions,” in Proc. of 6th Int. Memory Workshop, May 2014, pp. 1-4, doi:10.1109/IMW.2014.6849384 [PDF]

2013

  1. X. Fong, and K. Roy, “A hybrid spin-charge mixed-mode simulation framework for evaluating STT-MRAM bit-cells utilizing multiferroic tunnel junctions,” in Proc. of 2013 Int. Conf. on Simulation of Semicond. Processes and Dev. (SISPAD), Sep. 2013, pp. 372-375, doi:10.1109/SISPAD.2013.6650652 [PDF]
  2. X. Fong, and K. Roy, “Robust low-power multi-terminal STT-MRAM,” in Proc. of 13th Non-volatile Memory Technology Symposium (NVMTS), Aug. 2013, pp. 1-4, doi:10.1109/NVMTS.2013.6851056 [PDF]
  3. X. Fong, and K. Roy, “Low-power robust complementary polarizer STTMRAM (CPSTT) for on-chip caches,” in Proc. of  5th Int. Memory Workshop (IMW 2013), May 2013, pp. 88-91, doi:10.1109/IMW.2013.6582105 [PDF]
    • Errata
      1. Parameters in Table I should be: V_{DD}~=~1.4\text{V}
      2. Table II should have same values for CPSTT and SSCs: I_{C}~=~210{\mu}\text{A},~J_{C}~=~8.4\text{MA/cm}^{2}_{}
  4. M. Sharad, X. Fong, and K. Roy, “Exploring the design of ultra-low energy global interconnects based on spin torque switches,” in Proc. of IEEE Int. Electron Device Meeting (IEDM) 2013, Dec. 2013, pp. 32.6.1-32.6.4, doi:10.1109/IEDM.2013.6724739 [PDF]
  5. M. Sharad, R. Venkatesan, X. Fong, A. Raghunathan, and K. Roy, “Energy-efficient MRAM access scheme using hybrid circuits based on spin-torque sensors,” in Proc. of 2013 IEEE Sensors, Nov. 2013, pp. 2-7, doi:10.1109/ICSENS.2013.6688182 [PDF]
  6. M. Sharad, R. Venkatesan, X. Fong, A. Raghunathan, and K. Roy, “Reading spin-torque memory with spin-torque sensors,” in Proc. of 2013 IEEE/ACM Int. Symp. on Nanoscale Architectures (NANOARCH), Jul. 2013, pp. 40-41, doi:10.1109/NanoArch.2013.6623040 [PDF]

2012

  1. G. Panagopoulos, C. Augustine, X. Fong, and K. Roy, “Exploring variability and reliability of multi-level STT-MRAM cells,” in Proc. 70th Device Research Conference (DRC), Jun. 2012, pp. 139-140, doi:10.1109/DRC.2012.6257003 [PDF]
  2. C. Augustine, N. N. Mojumder, X. Fong, S. H. Choday, S. P. Park, and K. Roy, “STT-MRAMs for future universal memories: Perspective and prospective,” in Proc. 28th Int. Conf. on Microelectronics (MIEL), May 2012, pp. 349-355, doi:10.1109/MIEL.2012.6222872 [PDF]

2011

  1. X. Fong, S. K. Gupta, N. N. Mojumder, S. H. Choday, C. Augustine, and K. Roy, “KNACK: a hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells,” in Proc. of  2011 Int. Conf. on Simulation of Semicond. Processes and Dev. (SISPAD), Sep. 2011, pp. 51-54, doi:10.1109/SISPAD.2011.6035047 [PDF]
    • Errata
      1. Equation (4) should be: \frac{\partial\widehat{m}}{\partial t}=-\left|{\gamma_{}^{}}\right|\widehat{m}\times\left(\overrightarrow{H}_\text{EFF}+\overrightarrow{STT}\right)+{\alpha}\widehat{m}\times\frac{\partial\widehat{m}}{\partial t}
      2. Equation (11) should be: \overrightarrow{STT}_{}^{}=\frac{{\hbar}g\left(\widehat{m}\cdot\widehat{m}_{p}\right)J_{MTJ}}{2q{\mu}_{0}M_{S}t_{FL}}\left(\widehat{m}\times\widehat{m}_{p}\right)+\epsilon'\frac{{\hbar}J_{MTJ}}{2q\mu_{0}M_{S}t_{FL}}\widehat{m}_{p}

2010

  1. C. Augustine, X. Fong, and K. Roy, “Dual ferroelectric capacitor architecture and its application to TAG RAM,” in Proc. of IEEE Int. Conf. on Integrated Circuit Design Technology (ICICDT) 2010, Jun. 2010, pp. 24-38, doi:10.1109/ICICDT.2010.5510750 [PDF]

2009

  1. C. Augustine, X. Fong, B. Behin-Aein, and K. Roy, “A comprehensive nano-magnet based logic synthesis for ultra-low power digital systems,” SRC TECHCON 2009 (Best Paper in Session Award)
  2. C. Augustine, B. Behin-Aein, X. Fong, and K. Roy, “A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems,” in Proc. of 14th Asia and South Pacific Design Automation Conf. (ASP-DAC) 2009, Jan. 2009, pp. 847-852, doi:10.1109/ASPDAC.2009.4796586 [PDF]

2006

  1. A. Raychowdhury, X. Fong, Q. Chen, and K. Roy, “Analysis of super cut-off transistors for ultralow power digital logic circuits,” in Proc. of 2006 Int. Symposium on Low Power Electronics and Design (ISLPED), Oct. 2006, pp. 2-7, doi:10.1109/LPE.2006.4271798 (Best Paper Award) [PDF]

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